A NAND Flash is a non-volatile random access memory suitable for storing large volume data. Different NAND Flashes have different configuration types (also known as “specifications”), which is specifically embodied in a difference of the following one or more parameters: a maximum error checking and correction (ECC) capability, a pagesize, a blocksize, and the like.
The NAND Flash can implement various functions only under control of a control chip, such as a startup function, a data writing function, and a data reading function. A control over the NAND Flash by the control chip needs to comply with a configuration type of the NAND Flash to implement matching configuration. For example, it is required to meet the maximum ECC capability of the NAND Flash and read data according to the pagesize required by the NAND Flash. At present, generally before the NAND Flash is controlled to start up, pin information of the control chip is configured manually, so that the control chip learns the configuration type of the NAND Flash, and further controls, according to the configuration type of the NAND Flash, the NAND Flash to start up and implement various functions.
In the foregoing implementation process of controlling memory startup, the inventor finds that at least the following problem exists in the prior art: In a solution in which pin information of a control chip is manually configured, more pins need to be configured for the control chip (for example, three pins are used to configure the pagesize, two pins are used to configure the blocksize, and four pins are used to configure the maximum ECC capability), that is, more pins need to be used, which results in high costs.